搜索资源列表
sdram
- 文件中包含Sdram的Verilog程序以及很全的Sdram的资料-Sdram the Verilog file contains procedures and information are all of Sdram
sdram
- 使用VERILOG访问SRAM的程序，有需要的可以拿来借鉴-SRAM using VERILOG access procedures can be used in need of reference
XAPP134_SDRAM_Verilog
- Xilinx XAPP134 SDRAM Verilog
X-HDL
- 一款可以在verilog和VHDL之间互换的工具，经测试，暂无bug-A verilog and VHDL can be exchanged between the tools, tested, no bug
SDRAM-Verilog-HDL
- SDRAM控制器Verilog HDL-source-code.rar-SDRAM-controller-Verilog HDL-source-code.rar
SDR_SDRAM_IP
- SDR SDRAM 控制器，Altera官网重要资料。内涵说明文档，和VHDL与Verilog两种设计IP。-SDR SDRAM controller from Altera
sdram_control
- FPGA 用verilog控制sdram读写-FPGA control with verilog sdram read and write
4port-sdram
- 4端口SDRAM控制器verilog程序-4-port SDRAM controller with verilog
UART_DMA
- 基于DE1的nios的串口sdram通信例程-Based on DE1' s nios serial communication routines sdram
sdram
- 在ISE环境中，利用verilog语言编写的SDRAM的控制，已经通过功能仿真，其中PLL部分并没有加入，使用时可以自行加入PLL模块。-Verilog language in the ISE environment, the use of SDRAM control, through functional simulation, which the PLL part and did not join, can join the PLL blocks.
sdram_mdl
- verilog实现SDRAM控制器，quartus工程-verilog SDRAM controller, quartus project
sdram-ctrl
- FPGA sdram 全页模式控制，用verilog语言写的，非常的精简，控制方便-FPGA sdram full-page mode control, written in verilog language is compact, easy to control
DDR-SDRAM
- ddr sdram 控制器的源代码，内有vhdl和verilog。-DDR SDRAM controller
SDRAM
- 在nios环境下，结合verilog语言开发，功能是往SDRAM里面写0-99并打印出来-Nios environment, combined with the verilog language development function is to write to the SDRAM inside 0-99 and print out
sdram
- sdram控制器的Verilog描述 测试可用-the sdram controller Verilog descr iption of test available
DDR+SDRAM控制器verilog代码及中文说明文档
- DDR SDRAM控制器代码，不可多得的源代码。内附详细说明文档。
SDRAM
- SDRAM的verilog程序，很好地程序，希望大家支持-SDRAM verilog program, a good program, I hope you will support
dab1814114c3
- 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Descr iption ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route
verilog
- it is xilinx SDR SDRAM controller core
ddr-sdram
- It is complete document for DDR SD RAM program in verilog hdl